The present invention relates to a semiconductor device. Particularly, the invention is concerned with a technique effective in its application to a semiconductor device wherein two semiconductor chips are stacked and sealed with a single resin seal member.
A semiconductor device called MCP (Multi Chip Package) is known. Various structures of MCP type semiconductor devices have been developed and commercialized, among which one comprising two semiconductor chips stacked and incorporated in a single package is most popular. For example, in Japanese Unexamined Patent Publication No. Hei 2(1990)- 5455 (prior art literature 1) there is disclosed an MCP type semiconductor device wherein a chip for EEPROM (Electrically Erasable Programmable Read Only Memory) which contains a non-volatile memory unit as a memory chip is stacked on a chip for a microcomputer which contains a processor unit adapted to operate in accordance with a program, and these two chips are sealed with a single resin seal member. In the prior art literature 1 is disclosed a technique wherein a chip for a microcomputer and leads arranged around the microcomputer chip are electrically connected with each other by bonding wires, while an electrical connection between the microcomputer chip and the EEPROM chip is made by bumps.
In Japanese Unexamined Patent Publication No. Hei 5(1993)-343609 (prior art literature 2) is disclosed an MCP type semiconductor device wherein a bipolar chip which contains a circuit consisting mainly of a bipolar transistor is stacked on a CMOS (Complementary MOS) chip which contains a circuit consisting mainly of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and these two chips are sealed with a single resin seal member. In the prior art literature 2 is disclosed a technique wherein an electrical connection between the CMOS chip and leads arranged around the CMOS chip is made using bonding wires, and an electrical connection between the CMOS chip and the bipolar chip is made using bonding wires.